Vector-logic computing for faults-as-address deductive simulation

نویسندگان

چکیده

The aim of the research is to create logic-free vector computing, leveraging read-write transactions in memory, solve problems modeling and simulation stuck-at-fault combinations for complex logic elements digital structures. At same time, problem creating smart data structures based on logical vectors, truth tables, deductive matrices considered simplify algorithms parallel simulation. Vector computing a computational process bits binary functionality, where input faults are addresses bits. A method synthesis vectors propagating fault lists proposed, which has quadratic complexity transactions. Deductive combined into matrix, represent explicit single multiple stuck-at-faults. initial information constructing matrix bit-recoding matrix. Matrix easily obtained using recursive procedure combinatorial properties table. Considering emerging trends, focused in-memory an algorithm fault, as addresses, placed memory. proposed not use commands powerful processors.

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ژورنال

عنوان ژورنال: International Journal of Robotics and Automation (IJRA)

سال: 2023

ISSN: ['2722-2586', '2089-4856']

DOI: https://doi.org/10.11591/ijra.v12i3.pp274-288